Conventionally, in large-scale computer systems, data is managed by a dedicated data input/output device that is structured separately from a host computer. Among such data input/output devices is a storage device that forms a group of Redundant Arrays of Independent (or Inexpensive) Disks (RAID) with a plurality of hard disk devices (i.e., storage media) so as to improve reliability of data that is handled and the accessibility to the data.
Generally speaking, such a storage device improves the accessibility to the data by performing a write process (i.e., a writing process) while using a method called a write-back method. More specifically, in the case where the storage device has received a data write instruction from a host computer, which is a superordinate device of the storage device, the storage device notifies the host computer that the write process has been completed at a point in time when the data has been stored into a cache memory. After that, at a point in time when a predetermined condition has been satisfied, the data stored in the cache memory is stored into the hard disk device. By using the write-back method, it is possible to realize a data-access performance that is at a higher speed than in a situation where a write-through method is used. According to the write-through method, the host computer is notified that a write process has been completed after the writing of the data to the hard disk device has been completed.
Storage devices that use the write-back method as described above have a possibility of losing data if the electric power source is turned off without performing a normal shut-down operation due to a power outage or the like, while the data stored in the cache memory has not yet been stored into the hard disk device. (The electric power source being turned off without a normal shut-down operation will be hereinafter referred to as an “abnormal shut-down”.) The reason is that the cache memory is usually structured with a volatile memory and thus loses the data therein when the electric power supply from the electric power source is stopped.
To cope with this situation, some storage devices are structured in such a manner that, in the case where an abnormal shut-down has occurred, the data in the cache memory is saved into a nonvolatile memory while electric power is being supplied from a large-capacity capacitor that is able to supply the electric power even after the electric power source has been turned off so that, when the electric power source is turned on after the abnormal shut-down, the data saved in the nonvolatile memory is restored into the cache memory. A battery device may be used in place of a capacitor; however, because battery devices have the problem of degradation of battery cells or the like, there is a tendency that capacitors, which degrade less from electrical charging and discharging, are more popularly used in recent years.
As explained above, the storage devices that use the write-back method are able to realize a high-speed access performance to the host computer and are able to prevent the data from being lost when an abnormal shut-down has occurred. As to the examples of the above-described technology, see Japanese Laid-open Patent Publication No. 2004-506256 and Japanese Laid-open Patent Publication No. 2001-092648, for example.
The conventional storage devices described above, however, have a problem where a large-scale data transfer circuit needs to be used so as to allow the data transfer processes at a high speed when an abnormal shut-down has occurred and when the storage device starts up after an abnormal shut-down.
More specifically, to perform the data transfer processes at a high speed, it is a good idea to provide, in dual manner, two data transfer circuits that perform the process of saving the data in the cache memory into a nonvolatile memory (hereinafter, a “data saving process”) and two data transfer circuits that perform the process of restoring the data saved in the nonvolatile memory into the cache memory (hereinafter, a “data restoring process”), so that the data transfer processes are performed in parallel; however, this structure has a problem that the circuit scale becomes large.
If it is possible to perform the data saving process at a higher speed, it will be possible to save a larger volume of data into a nonvolatile memory in a short period of time during which the electric power is supplied from the capacitor. Further, if it is possible to perform the data restoring process at a higher speed, it will be possible to shorten the time period it takes for the storage device to start up after an abnormal shut-down. For these reasons, it is desirable that the data transfer processes described above be performed at a high speed.
In recent years, it has been common practice to realize data transfer circuits by using Field Programmable Gate Arrays (FPGAs) for the purpose of reducing development man-hours or the like. To realize the four data transfer circuits described above by using such an FPGA, it is necessary to use an FPGA that has, again, a large scale. Thus, problems arise where an FPGA having a large installation area needs to be installed into the storage device and where the cost increases. Making storage devices compact and reducing the cost have become common goals. Increases in the installation area and in the cost are problematic.
As explained above, in the field of storage devices, it has been a focus of attention how to realize a technique for efficiently performing the data saving process and the data restoring process without the need to enlarge the data transfer circuits.